Data streams that transmitted between communication systems often include both a data portion and a clock signal. At a receiving system, the data portion is extracted (i.e., recovered) from the data stream and the clock signal is also extracted from the data stream. The circuit that performs these extractions is called a clock and data recovery circuit (“CDR”).
A CDR may be susceptible to jitter (i.e., noise) and, as Input/Output (“I/O”) rates scale beyond several gigabits per second, the use of external test equipment to accurately characterize and quantify link operating margins (i.e., a CDR's ability to distinguish between data and jitter) becomes increasingly difficult. FIG. 1 illustrates a conventional test bench for testing a CDR 103. The test bench comprises external test equipment, such as a pattern generator 101 and a modulation source 102, which are expensive to purchase. As illustrated, the CDR 103 may be a component of a circuit package 104, and the circuit package 104 may be coupled to a circuit board 105. While testing jitter tolerance through external test equipment is useful, and currently required by industry specifications, it is not always an effective measure of the CDR's 103 performance because external test equipment may not accurately reflect internal components of a system being tested.